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| CML Semiconductor Products PRODUCT INFORMATION FX009A Low-Noise Digitally Controlled Amplifier Array Publication D/009A/3 July 1994 Features/Applications 8 Digitally Controlled Low-Noise Amplifiers 15 Gain/Attenuation Steps 7 Trimmers, with a 3dB Range in 0.43dB Steps 1 'Volume' Trimmer, with a 14dB Range in 2.0dB Steps SERIAL CLOCK INPUT 8 - BIT SERIAL DATA INPUT AND LINE DECODERS 8-Bit Serial Data Control Output Mute/Powersave Function Audio and Data Gain Control Applications Cellular, PMR, PABX Applications LOAD/LATCH SERIAL DATA INPUT V DD V BIAS 16 LOAD/LATCH 7 8 1 2 3 4 5 6 1 16-LINE STEP CONTROLS TO AMPLIFIERS 1 to 8 V SS 5 Ch1 2 V BIAS *OUTPUT MUTE - POWERSAVE * V BIAS Ch5 6 Ch2 3 V BIAS * * V BIAS Ch6 7 FX009A Ch3 V BIAS * * VBIAS Ch7 4 8 Ch4 V BIAS * * V BIAS Ch8 4 3 2 1 5 6 7 8 - VOLUME CONTROLLED AUDIO OUTPUT LINES Fig.1 Functional Block Diagram Brief Description The FX009A Digitally Adjustable Amplifier Array is intended to replace trimmer potentiometers and volume controls in Cellular, PMR, Telephony and Communications applications where d.c., voice or data signals need adjustment. The FX009A is a low-noise single-chip LSI consisting eight digitally controlled amplifier stages, each with 15 distinct gain/attenuation steps. Control of each individual amplifier is by an 8-bit serial data stream. Seven of the amplifier stages offer a +/-3dB range in steps of 0.43dB, whilst the remaining amplifier offers a +/-14dB range in steps of 2dB, and is intended for volume control applications. Each amplifier includes a 16th 'Mute' state which sets the output to bias (VDD/2) and powersaves the entire section. Minimum current drain may be achieved by muting all eight sections. 1 This product replaces the need for manual trimming of audible signals by using the host microprocessor to digitally control the set-up of all audio levels. Applications include: (i) Control, adjustment and set-up of communications equipment by an Intelligent ATE without manual intervention - eg. Deviation, Microphone and L/S Level, Rx Audio Level etc. (ii) Automatic Dynamic Compensation of drift caused by variations in temperature, linearity, etc. (iii)Fully automated servicing and re-alignment. The FX009A is a low-power, single 5-volt CMOS device available in both 24-pin DIL and SMD package versions. Pin Number FX009A J 1 2 FX009A LG/LS 1 2 Function Serial Clock : This external clock pulse input is used to "clock in" the Control Data. See Figure 4, Data Load Timing. This input has an internal 1M pullup resistor. Load/Latch : Governs the loading and execution of the control data. During serial data loading this input should be kept at a logical '0' to ensure that data rippling past the latches has no effect. When all 8 bits have been loaded, this input should be strobed '0' '1' '0' to latch the new data in. Data is executed on the falling edge of the strobe. If the Load/Latch input is used this pin should be left open circuit. This input has an internal 1M pullup resistor. Load/Latch : The inverted Load/Latch input. This function governs the loading and execution of the control data. During serial data loading this input should be kept at a logical '1' to ensure that data rippling past the latches has no effect. When all 8 bits have been loaded, this input should be strobed '1' - '0' - '1' to latch the new data in. Data is executed on the rising edge of the strobe. If the Load/Latch input is used this pin should be left open circuit. This input has an internal 1M pulldown resistor. Ch1 Input : Ch2 Input : Ch3 Input : Ch4 Input : Analogue Inputs : These individual amplifier inputs are self-biasing, a.c. input analogue signals must be capacitively coupled to these pins, as shown in Figure 2. In the powersave modes the inputs are biased at VDD/2. Note that amplifiers Ch1 to Ch8 are 'inverting amplifiers.' 3 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VBIAS : The output of the on-chip bias circuitry, held at VDD/2. This pin should be decoupled to VSS as shown in Figure 2. Ch5 Input : Ch6 Input : Ch7 Input : Ch8 Input : VSS : Negative supply rail (GND). Ch8 Output : Ch7 Output : Ch6 Output : Ch5 Output : Analogue Outputs : The individual "Gain Controlled" amplifier outputs. Ch1 to Ch7 range from -3dB to +3dB in 0.43dB steps, Ch8 could be utilized as a volume control, ranging from -14dB to +14dB in 2.0dB steps. In the powersave mode the selected output is biased at VDD/2. Analogue Inputs : No internal connection. Do not use. Ch4 Output : Ch3 Output : Ch2 Output : Ch1 Output : VDD : Positive supply rail. A single +5-volt power supply is required. Control Data Input : Operation of the 8 amplifier channels (Ch1 - Ch8) is controlled by the 8 bits of data entered serially at this pin . The data is entered (bit 7 to bit 0) on the rising edge of the external Serial Clock. The data format is described in Tables 1, 2 and Figure 4. This input has an internal 1M pullup resistor. Analogue Outputs Note that amplifiers Ch1 to Ch8 are 'inverting amplifiers.' 2 Application Notes V DD C 10 V SS SERIAL CLOCK INPUT LOAD/LATCH LOAD/LATCH CHANNEL 1 INPUT CHANNEL 2 INPUT CHANNEL 3 INPUT CHANNEL 4 INPUT C4 V BIAS C2 C3 C1 1 2 3 4 5 6 7 C5 C6 C7 C8 8 9 10 11 12 24 23 22 21 V DD CHANNEL 1 OUTPUT CHANNEL 2 OUTPUT CHANNEL 3 OUTPUT CHANNEL 4 OUTPUT X SERIAL CONTROL DATA INPUT FX009A J - LG - LS 20 19 18 17 16 15 14 13 V SS CHANNEL 5 OUTPUT CHANNEL 6 OUTPUT CHANNEL 7 OUTPUT CHANNEL 8 OUTPUT CHANNEL 5 INPUT CHANNEL 6 INPUT CHANNEL 7 INPUT CHANNEL 8 INPUT C9 Notes (1) Channel Amplifiers 1 to 8 are inverting amplifiers. (2) Analogue input capacitors C1 to C8 are only required for a.c. input signals, d.c. input signals do not require these components. V SS Component C1 to C8 C9 C10 Tolerances: C = 20% Unit Value 0.1 1.0 1.0 Fig.2 External Component Connections Application Recommendations To avoid excess noise and instability in the final installation it is recommended that the following points be noted. (a) A noisy or badly regulated power supply can cause instability and/or variance of selected gains. (b) Care should be taken on the design and layout of the printed circuit board. (c) All external components (Figure 2) should be kept close to the FX009A package. (d) Inputs and outputs should be screened wherever possible. (e) Tracks should be kept short. (f) Analogue tracks should not run parallel to digital tracks. (g) A "Ground Plane" connected to VSS will assist in eliminating external pick-up on the channel input and output pins. (h) Do not run high-level output tracks close to lowlevel input tracks. (i) Input signal amplitudes should be applied with due regard to Figure 3. SINAD (dB) 60 50 Input Frequency = 1.0kHz Input Level 0dB ref: = 775mVrms Ch1 to Ch8 Gain Set to 0dB 40 1000.0 30 -40 10.0 25.0 75.0 110.0 250.0 775.0 1730.0 mVrms 7 -30 -20 -17 -10 0 dB Fig.3 SINAD vs Input Level - Typical Values 3 INPUT LEVEL The gain of each amplifier block (Channel 1 to Channel 8) in the FX009A is set by a separate 8-bit data word ( bit 7 to bit 0 ). This 8-bit word, consisting of 4 Address bits (bit 7 to bit 4) and 4 Gain Control bits (bit 3 to bit 0), is loaded to the Control Data Input in serial format using the external data clock. Data is loaded to the FX009A on the rising edge of the Serial Clock. Loaded data is executed on the falling (rising) edge of the Load/Latch (Load/Latch) pulse. Table 1 shows the format of each 4-bit Address word, Table 2 shows the format of each Gain Control word with Figure 4 describing the data loading operation and timing. Table 1 Address Word Format Bit 7 MSB 1 1 1 1 1 1 1 1 Bit 6 0 0 0 0 1 1 1 1 Bit 5 0 0 1 1 0 0 1 1 Bit 4 LSB 0 1 0 1 0 1 0 1 Channel Selected 1 2 3 4 5 6 7 8 Table 2 Gain Control Word Format Bit 3 MSB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 LSB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Stage 1 to 7 (0.43dB) Powersave -3.0 -2.571 -2.143 -1.714 -1.286 -0.857 -0.428 0 0.428 0.857 1.286 1.714 2.143 2.571 3.0 Stage 8 (2.0dB) Powersave -14.0 dB -12.0 dB -10.0 dB -8.0 dB -6.0 dB -4.0 dB -2.0 dB 0 dB 2.0 dB 4.0 dB 6.0 dB 8.0 dB 10.0 dB 12.0 dB 14.0 dB Data Loading The 8-bit data word is loaded bit 7 first and bit 0 last. Bit 7 must be a logic "1" to address the chip. If bit 7 in the word is a logic "0" that 8-bit word will not be executed. Figure 4 (below) shows the timing information required to load and operate this device. SERIAL DATA CLOCK t PWH t PWL SERIAL DATA IN (ONE 8-BIT WORD) t DS tDH Loaded Last BIT 6 BIT 1 BIT 0 8th Clock Pulse Next Clock Pulse Logic '1' Loaded First BIT 7 LOAD/LATCH t LLD t LLW t LLO LOAD/LATCH Timing tPWH Serial Clock "High" Pulse Width tPWL Serial Clock "Low" Pulse Width tDS Data Set-up Time tDH Data Hold Time tLLD Load/Latch Delay tLLW Load/Latch Pulse Width tLLO Load/Latch Over Time Fig.4 Serial Control Data Loading Diagram 4 Specification Absolute Maximum Ratings Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -0.3 to 7.0V Input voltage at any pin (ref VSS = 0V) -0.3 to (VDD + 0.3V) Sink/source current (supply pins) +/- 30mA (other pins) +/- 20mA Total device dissipation @ TAMB 25C 800mW Max. Derating 10mW/C Operating temperature range: FX009A J -30C to +85C (cerdip) FX009A LG/LS -30C to +70C (plastic) Storage temperature range: FX009A J -55C to +125C (cerdip) FX009A LG/LS -40C to +85C (plastic) Operating Limits All device characteristics are measured under the following conditions unless otherwise specified: VDD = 5.0V, TAMB = 25C. Audio Level 0dB ref: = 775mVrms. Amplifier Gain Set = 0dB. Characteristics See Note Min. Typ. 5.0 0.16 3.75 Max. 5.5 - - Unit V mA mA Static Values Supply Voltage (VDD) 4.5 Supply Current - - All Stages Quiescent - - All Stages Operating - Dynamic Values Control Functions Input Logic '1' 3.5 Input Logic '0' - Digital Input Impedances 0.5 Amplifier Stages (General) Bandwidth (-3dB) 15.0 Output Impedance - Total Harmonic Distortion 1 - Output Noise Level (per stage) 2 - Onset of Clipping 3 - Gain Variation 4 - Interstage Isolation - "Trimmer" Stages (Ch1 - Ch7) Gain -3.0 Gain per Step (15 in No.) - Step Error 5 - Input Impedance 100.0 "Volume" Stage (Ch8) Gain -14.0 Gain per Step (15 in No.) - Step Error 5 - Input Impedance 50.0 Timing (Figure 4) Serial Clock "High" Pulse Width (tPWH) 250 Serial Clock "Low" Pulse Width (tPWL) 250 Data Set-up Time (tDS) 150 Data Hold Time (tDH) 50 Load/Latch Over Time (tLLO) - Load/Latch Delay (tLLD) 200 Load/Latch Pulse Width (tLLW) 150 Serial Data Clock Frequency - Notes 1. Gain Set 0dB, Input Level 1kHz -3.0dB (549mVrms). 2. a.c short-circuit input, measured in a 30kHz bandwidth. 3. See Figure 3. 4. Over temperature and supply voltage range. 5. With reference to a 1.0kHz signal. 5 - - 1.0 - 0.8 0.35 65.0 1.73 - 60.0 - 1.5 - - 3.0 0.5 - 0.1 - +3.0 - 0.2 - +14.0 - 0.4 - - - - - 50.0 - - 2.0 V V M kHz k % Vrms Vrms dB dB dB dB dB k dB dB dB k ns ns ns ns ns ns ns MHz 0.43 - - 2.0 - - - - - - - - - - Package Outlines The FX009A is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagrams and pins on all package styles number anticlockwise when viewed from the top. Handling Precautions The FX009A is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage. FX009AJ 24-pin cerdip DIL (J4) FX009ALG 24-pin quad plastic encapsulated bent and cropped (L1) NOT TO SCALE NOT TO SCALE Max. Body Length Max. Body Width 32.00mm 13.36mm Max. Body Length Max. Body Width 10.25mm 10.25mm FX009ALS 24-lead plastic leaded chip carrier (L2) NOT TO SCALE Ordering Information FX009AJ 24-pin cerdip DIL (J4) FX009ALG 24-pin quad plastic encapsulated bent and cropped (L1) FX009ALS 24-lead plastic leaded chip carrier (L2) Max. Body Length Max. Body Width 10.40mm 10.40mm CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry. 6 CML Microcircuits COMMUNICATION SEMICONDUCTORS CML Product Data In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached. Company contact information is as below: CML Microcircuits (UK)Ltd COMMUNICATION SEMICONDUCTORS CML Microcircuits (USA) Inc. COMMUNICATION SEMICONDUCTORS CML Microcircuits (Singapore)PteLtd COMMUNICATION SEMICONDUCTORS Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com 4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com D/CML (D)/1 February 2002 |
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